Verification Techniques for System-Level Design / Masahiro Fujita

Book Cover Verification Techniques for System-Level Design
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/ Masahiro Fujita
Publisher: Morgan Kaufmann
Availability:Usually ships in 24 hours
Sales Rank: 99999999
ISBN-10: 0124054617
ISBN-13: 9780124054615


This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
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