Structured Logic Design with VHDL

KEY BENEFIT: Previous books on this subject have concentrated just on the VHDL hardware description language without really teaching the design, process. This new reference really shows how to design with VHDL in a synthesis context. KEY TOPICS: Unlike the other books, it teaches the VHDL language in detail and gives numerous examples of VHDL models used in different aspects of the design process; describes design at three different levels of abstraction: algorithmic, data flow, and gate level; illustrates the design of combinational and sequential logic at these three levels; and illustrates various forms of control unit design. For practicing engineers involved in digital design and those interested in the development of methods for computer aided design.