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Self-Testing VLSI Design
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Description
The present study provides a current review on the problems of self-test VLSI design. A summary is given on self-test VLSI design results that have been obtained by scientists in leading scientific centres for computer integrated circuits. Emphasis is placed on the theoretical fundamentals of designing self-test VLSI building blocks such as built-in test generators and output response analyzers. Particular attention is paid to: Structural design of self-test VLSI circuits; design of universal modules for self-test VLSI circuits; and examination of the VLSI circuits for signature testability. It has been clearly demonstrated that the design-for-testability techniques employed by this method provide ideal conditions for the straightforward implementation of self-test concepts. The work will prove essential reading for all those interested in both the basic facts and current research in this field.









