Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits.

A new jitter reduction technique is proposed for reducing the timing jitter in a serializer-deserializer (SERDES) circuit. The technique involves transmit and receive side jitter reducer circuits made of only 14 and 20 transistors, respectively. They reduce the jitter in the clock generated by the phase-locked-loop (PLL) at the transmit side, and the jitter between the recovered clock and the serial data at the receive side. The jitter reducers are designed using 70nm Berkeley Predictive process models and tested with various types of input jitter. In the case of the transmit side jitter reducer, the jitter is reduced, on average, by 62.24%. The performance of the jitter reducer is compared with the adaptive PLL technique proposed by Xia et al. [39] in terms of the peak-to-peak jitter reduction. The peak-to-peak jitter is reduced, on average, by 45.51% using the transmit side jitter reducer. For the receive side jitter reducer, the jitter is reduced, on average, by 35.88%. The SERDES circuit is then tested for its jitter performance under three conditions: (1) no jitter reducers are present, (2) the receive side jitter reducer is present and (3) both transmit and receive side jitter reducers are present. In each of these cases, the bit-error rate (BER) is computed probabilistically and is shown to improve from 8.3 x 10 -2 to 6.44 x 10-20, for input RMS periodic jitter (PJ) of 71.77 ps. Finally, a SERDES test scheme is used to test the jitter reducers for their stuck-at faults and then to perform the receiver jitter tolerance and BER tests.