Networks on Chip: Topology, Switching, Routing

Network-on-Chip (NoC) is communication infrastructure for future multi-core Systems-on-Chip (SoCs). NoCs are expected to overcome scalability and performance limitations of Point-to-Point (P2P) and bus-based communication systems. The routing algorithm of a given NoC affects the performance of the system measured with respect to metrics such as latency, throughput and load distribution. In this work, the popular Orthogonal One Turn (O1TURN) and Dimension Order Routing algorithms (DOR) for 2D-meshes are implemented by computer simulation. Investigation of the effect of parameters such as packet, buffer, and topology sizes on the performance of the network showed that the center of the network is loaded more than the edges. A DOR algorithm with modified flit injection policy is evaluated to achieve a more balanced load distribution. This book explains basic concepts of On-Chip Networks and can be used as an introductory material.