WIRE AWARE CACHE ARCHITECTURE: MANAGING WIRES AT THE ARCHITECTURE LEVEL

Technology scaling has resulted in a steady increase in transistor speed. However, unlike transistors, global wires that span across the chip show a reverse trend of getting slower with shrinking process. Modern processors are severely constrained by wire delay and the widening gap between transistors and wires will only exacerbate the problem. Following the traditional design approach of adopting a single design point for all global wires will be suboptimal in terms of both power and performance. VLSI techniques allow several wire implementations with varying latency, power, and bandwidth properties. The dissertation advocates exposing wire properties to architects and demonstrates that prudent management of wires at the microarchitectural level can lead to significant improvement in power and delay characteristics of future communication bound processors. A heterogeneous interconnect (composed of wires with different latency, bandwidth, and power characteristics) is proposed that leverages varying latency and bandwidth needs of on-chip global messages to alleviate interconnect overhead.