Hardware-Fault-Tolerant Data Processing: Model-based Reliability Evaluation Of Data Processing In HW-Fault-Tolererant Processor Systems

The complexity and functionality of electronic control units have more and more increased the last years. In addition, the requirements of these systems became harder in terms of safety. However, the development of present microcontrollers follows the trend of decreasing feature size that leads to less reliability, arbitrary hardware faults are more likely. This lack of reliability is often compensated by several pure software-based approaches using error detecting codes. The coded processing uses arithmetic codes to detect arbitrary faults during the calculation of results in processing units of a microcontroller. Further, related works often proof the effectivity of the used code by experimental methods. Sufficient models for analytical evaluations are not known. Thus, this work discusses the approach of model-based reliability evaluation of arithmetic operations in a processor system.