Monotonic Static CMOS: A Design Approach for Sub-100nm Technologies with Significant Gate Leakage

As CMOS technologies continue to scale well into sub-100nm, there are a number of effects that might change the tradeoffs involved in logic circuit implementation. If gate oxide thicknesses continue to shrink in the absence of other modifications, gate leakage currents will become more significant than subthreshold leakage. This would exacerbate the growing problem of energy consumption, significantly increasing static power. In addition, gate leakage currents would have a negative impact on noise margins. This could very well have an impact on the tradeoffs between various choices of logic gate implementations. In this thesis, I explore the performance of monotonic static logic circuits in this environment and their applications in high performance low power VLSI circuits. The main goal of this thesis is to provide a set of data to show the usefulness of MS-CMOS logic family in sub-100nm CMOS technologies. It is further intended to show that MS-CMOS can be used along with static CMOS to achieve a wider range of tradeoffs in VLSI circuits.