IEC 61691-5 Ed. 1.0 en:2004, Behavioural languages - Part 5: VITAL ASIC (application specific integrated circuit) modeling specification

Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard