Field Programmable Gate Array (FPGA) Based Software Defined Radio (SDR) Design

There are existing wideband communications systems that were built using field programmable gate array (FPGA)- based software defined radio (SDR) designs. Despite the inherent advantages of these systems, some are functionally restricted by limited output bandwidth. This thesis was conceived in order to mitigate the restrictions imposed on such designs. This was accomplished by designing an FPGA-based SDR that can compress sampled intermediate frequency (IF) signals. The compression scheme used in the final design is based on flexible operator-defined timefrequency bins and independent energy thresholds for each bin. The thesis presents basic design concepts that influenced the development process, the final design implementation created using Xilinx’s System Generator software, and the tests used to verify the final design’s functional capabilities.