FPGA Design Engineering Project Course: With VHDL

This is a project course for FPGA Designers that focuses on the VHDL Description Language that targets programmable logic and ASIC Design. You will learn the usage of the language in representation, simulation, verification, and synthesis with respect to extensive real-world examples. Essential syntax and semantics of the VHDL language including design entity, architectural bodies, concurrent and sequential statements, processes, data types, packages, configurations, and register transfer level design are among the covered topics. Learn a skill that is in high demand. Learn how to do projects that you'd only see in the real-world. This course includes all the source code, snap shots, and full explanations. Topics include Image Processing, Text I/O, and more! This book is based on projects. The projects start easy and will get harder as the course goes on. In this e-book we do not cover the basics. We give you links that you can look up as a refresher. This e-book is best displayed on a computer. Go to http://www.amazon.com/gp/kindle/pc/download to download kindle for PC viewer.