{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for  ASIC and FPGA Design","author_name":"Stuart Sutherland","thumbnail_url":"https://www.ebooknetworking.net/books/154/677/big1546776346.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-1546776346.html\">RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for  ASIC and FPGA Design</a>","width":400,"height":300}