{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow","author_name":"Colin J. Ihrig","thumbnail_url":"https://www.ebooknetworking.net/books/363/910/big3639106903.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-3639106903.html\">Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow</a>","width":400,"height":300}