{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"Design and Modeling of PLL Based CDR for Inter Chip Communications: Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery ... Gb/s Intra/Inter Chip Communications in SoC","author_name":"Maher Assaad","thumbnail_url":"https://www.ebooknetworking.net/books/363/918/big3639185544.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-3639185544.html\">Design and Modeling of PLL Based CDR for Inter Chip Communications: Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery ... Gb/s Intra/Inter Chip Communications in SoC</a>","width":400,"height":300}