{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"A HDL & Verilog Code: Simulated Output","author_name":"Manu Sudhan, Manjunatha S.","thumbnail_url":"https://www.ebooknetworking.net/books/384/842/big3848423243.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-3848423243.html\">A HDL &amp; Verilog Code: Simulated Output</a>","width":400,"height":300}