{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"Advanced HDL Synthesis and SOC Prototyping: RTL Design using Verilog","author_name":"Vaibbhav Taraate","thumbnail_url":"https://www.ebooknetworking.net/books/981/108/big981108775X.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-981108775X.html\">Advanced HDL Synthesis and SOC Prototyping: RTL Design using Verilog</a>","width":400,"height":300}