{"version":"1.0","type":"rich","provider_name":"EbookNetworking","provider_url":"https://www.ebooknetworking.net","title":"[ INTRODUCTION TO LOGIC SYNTHESIS USING VERILOG HDL Paperback ] Reese, Robert ( AUTHOR ) Jun - 28 - 1905 [ Paperback ]","author_name":"Robert Reese","thumbnail_url":"https://www.ebooknetworking.net/books/noimage.jpg","thumbnail_width":330,"thumbnail_height":500,"html":"<a href=\"https://www.ebooknetworking.net/books_detail-B00UKLW8PY.html\">[ INTRODUCTION TO LOGIC SYNTHESIS USING VERILOG HDL Paperback ] Reese, Robert ( AUTHOR ) Jun - 28 - 1905 [ Paperback ]</a>","width":400,"height":300}