Nanometer SRAM and DRAM Circuit Design

Low power consumption is moving higher up on the priority list of system requirements resulting in low power memory architectures and circuit implementations.  Circuits need to operate reliably at low voltages (below 1.0V) yet meet their performance targets.  The larger spread of process variations as the technology node shrinks makes worst case design impractical.  These design challenges impact also the peripheral, control, ancillary and i/o circuits of the SRAM and DRAM.  The goal of this book is to describe circuits and circuit design methodologies which overcome these challenges.  Examples of scripts, which are used to steer the CAD tools, used in the analysis of the circuits and to gather and present the results of such analysis, are provided.  Since a variety of the emerging technologies such as CNT (Carbon Nano Tube) and FinFET are being developed and researched, a new design method for memory cell will also be discussed based on those emerging technologies.