The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

The UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM knowledge before a job interview to be able to confidently answer questions such as "What is a uvm_agent?" , "How do you use uvm_sequences?", and "When do you use the UVM's factory." The UVM Primer's downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on www.uvmprimer.com) to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM.

• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
• Cracking Digital VLSI Verification Interview: Interview Success
• RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
• A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition
• Digital Logic RTL & Verilog Interview Questions
• Logic Design and Verification Using SystemVerilog (Revised)
• Getting Started with UVM: A Beginner's Guide
• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
• Verilog by Example: A Concise Introduction for FPGA Design
• SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling