A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition

With both cookbook-style examples and in-depth verification background, novice and expert verification engineers will find information to ease their adoption of this emerging Accellera standard.

• The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology
• SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
• Digital Logic RTL & Verilog Interview Questions
• Cracking Digital VLSI Verification Interview: Interview Success
• Practical UVM
• Logic Design and Verification Using SystemVerilog (Revised)
• SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications
• Advanced UVM
• Getting Started with UVM: A Beginner's Guide
• Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)