Two-Tone PLL: Two-Tone PLL for On-Chip RF Test

In present era VLSI ICs, production test is becomming increasingly expensive. Especially in case of mixed signal/RF chips, it can even override the direct manufacturing expenses.Under this context built inself test(BiST)can be viable solution to overcome this problem, which so far not appreciated by chip industry.In this book the two tone PLL provides solution and this circuit is intende for on-chip test of RF blocks. The primary application is the third order intermodulation test(TOI), vital for RF front end. If the spectral analysis can also be completed by DSP available on the chip or on board it provides a built -in- selftest(BiST), which can replace costly test instrumentation(ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect, while keeping the two oscillation frequencyies close. The two-tone PLL has been designed and verified at the system level using verilog-A models in CadenceTM. Besides,two building blocks of the PLL were implemented at the circuit level in 90 nm CMOS technology.And this book is useful for professionals in the field of mixed-signal/RF IC.