Design Verification With E

E is a new hardware verificationlanguage, or hvl. Verification is one of the most time consuming and cumbersomeprocesses in hardware design. As designs grow more complex,the verification problems increase exponentially - when a design doubles insize, the verification effort can easily quadruple. In the past design teamshave used verilog and vhdl. E gives engineers the speed and efficiency they havebeen craving, while also allowing for simulation of other components as well. Design verification withe emphasizes breadth rather than depth. It imparts to the reader aworking knowledge of a broad variety of e-based topics, thus giving the reader aglobal understanding of e-based design verification. This book should beclassified not only as an e book but, more generally, as a design verificationbook. This book presents a logical progression of e-based topics. It startswith the basics, such as functional verification methodologies, e basics andthen gradually builds on to bigger examples and eventually reaches advancedtopics, such as coverage driven functional verification, re-usable verificationcomponents and c/c++ interface. Thus, the book is useful to e users with varyinglevels of expertise.