Logic Synthesis

Covers recent theoretical and algorithmic advances in synthesizing area-efficient, high-performance, testable VLSI circuits. Explores two-level and multilevel combinational logic synthesis and synthesis of testability. A complete description of state-of-the-art combinational logic optimization methods and their application to the reduction of circuit area is included. Timing analysis methods that compute the true critical delay of a circuit and optimization methods that target minimal circuit delay are also covered. Annotation copyright Book News, Inc. Portland, Or.