A fault tolerant FPGA architecture.

SRAM-based field programmable gate arrays (FPGAs) have gained a lot of popularity due to their on-line reconfigurable features. With such growing demand, manufacturers are constantly striving to build more densely packed FPGAs with higher logic capacity; this is likely to increase the probability of errors. The proposed architecture is capable of correcting faults in the FPGA cells within the same clock cycle. This architecture consists of an array of identical FPGA cells each of which may be used for logic functionality, for interconnections, or for both, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs. An FPGA cell can have different modes of operation and collectively a group of such cells can implement any logic function that is either registered or combinational. The built-in fault tolerance is capable of correcting, on an average, one error per cell where either the errors can result from permanent faults (such as stuck-at faults) or transient faults (errors resulting from radiation or other transient effects). Thus, an on-line fault tolerant FPGA architecture has been proposed that is more suited for tolerating transient faults within every FPGA cell in the same clock cycle. This feature is not available in any current commercially available FPGA devices.