Fault properties and their uses in testing digital integrated circuits.

Digital integrated circuits (ICs) must be tested to ensure that the ICs behave as specified. The most popular technique for testing digital ICs is structural testing. Structural test patterns are generated based on test metrics, which guide the selection of input stimuli and estimate the thoroughness of the test sets. Test metrics represent the thoroughness of test sets by fault coverage numbers, which typically reflect the percentage of faults tested. This dissertation shows that an individual fault has its own distinctive attributes, referred to as fault properties. They affect the generation and evaluation of the tests. Thus, fault properties can be exploited to improve both the generation procedure and the quality of structural test sets. Some properties are already widely used, whereas others are neglected during test generation. By establishing the concept of fault properties, the ground work for improving structural test generation is provided. This dissertation also presents two techniques for improving transition test quality by exploiting fault properties. The Launch-on-Shift-Capture (LOSC) transition test improves fault coverage over the conventional transition test, while, in most cases, reducing pattern counts. The Transition fault propagated to All Reachable Outputs (TARO) test improves the thoroughness of the transition test by testing each fault multiple times using different observation points. This dissertation presents the concepts and test generation methods as well as the experimental results of these two techniques.