Planar source pocket (PSP) tunnel MOSFET: Potential device solution for low power applications and improving tunneling MOSFET performance.

As MOSFET is scaled below 90nm, many daunting challenges arise. Short channel effects (DIBL and VTH roll-off), off-state leakage, parasitic capacitance and resistance severely limit the performance of these transistors. Moreover as the device dimensions are being scaled down into the nanometer regime, power dissipation is becoming a principal concern. Supply voltage scaling constraints and the diffusion limit of 60mv/dec on the sub-threshold swing (SS) lead to reduced ION/IOFF and high I OFF. This leads to higher active power dissipation and sub-threshold power consumption. To provide for a given overdrive and control power dissipation, lower threshold voltage is required while maintaining a low IOFF. This points to the pressing need for devices with steep (< 60mv/dec) sub-threshold behavior. New device innovations are essential to overcome these challenges. In recent years, research in novel devices (tunneling FETs, IMOS [1], [2]) for possible solutions towards providing steep sub-threshold behavior and improved ION at lower operating voltages has gained a lot of momentum. Most of the tunneling devices investigated have the configuration of gate controlled reverse biased p-i-n diodes ([3] - [8]]. Some of these devices have been shown to exhibit