Addressing Process Variations at the Microarchitecture and System Level

Technology scaling has resulted in an increasing magnitude of and sensitivity to manufacturing process variations. This has led to the adoption of statistical design methodologies as opposed to conventional static design techniques. At the same time, increasing design complexity has motivated a shift towards higher levels of design abstraction, i.e., microarchitecture and system level design. This monograph provides the reader with an introduction to recently proposed techniques that address one or more of these challenges. It surveys emerging statistical design techniques targeted towards the analysis and mitigation of process variation at the system level design abstraction, for both conventional planar and emerging 3D integrated circuits. The topics covered include variability macro-modeling for logic modules, system level variability analysis for multi-core systems, and system level variability mitigation techniques. The monograph uses illustrative and detailed examples to help explain the various techniques covered. It concludes with some pointers to future work that looks beyond conventional CMOS technology and highlights the relevance of system level variability analysis and mitigation techniques for emerging technologies.