Fault Diagnosis and Fault Tolerance: A Systematic Approach to Special Topics

With the rapid growth of scale of integration of VLSI chips and the need forreliable computers, fault diagnosis and fault tolerance have become important topics in chip design and manufacture. This book is intended to lead new researchers in the field to the frontier of some branches of the fault-tolerant computing field. The book presents the results of a research group working at Chongqing University, China, for the last twelveyears. It contains seven chapters that can be read independently of each other. Chapter 1 gives a mathematical introduction to four-valued logic and its applications to test generation, hazard identification, and transition logic. Chapter 2 summarizes work on the fault-diagnosis problem at the system level, with society diagnosis and an analog circuit as examples. Chapter 3 discusses the definition of a testability measure, introduces the synthesis problem for testability, and studies automatic design for testability at gate level and module level. Chapter 4 introduces the new NMRC (N-modular redundancy with comparing) technique and studies some optimal designs. Chapter 5 studies the fault-tolerance of interconnection switching networks and shows how networks can be designed to increase the tolerated number of faulty elements. Chapter 6 shows how fault-tolerance problems for multibus systems correspond to connectivity problems for hypergraphs and how optimal connectivity is achieved with BIB (balanced incomplete block) designs. Chapter 7 discusses TMR (triple modular redundancy) systems.