Novel Energy-Efficient Leakage Current Minimization Techniques: Self Controlling Cell-Based CMOS Circuit Topology

Leakage power loss is a major concern in deep-submicron technologies. For portable devices that have burst-mode type integrated circuits, it is acceptable to have leakage during the active mode. However, during the idle state it is wasteful to have leakage, as power is unnecessarily consumed with no useful work being done. In this work, a combination of high-threshold and standard-threshold sleep transistors embedded within the CMOS topology was used in voltage balancing of the Pull-Up Network (PUN) as well as the Pull-Down Network (PDN), thereby shutting them off and minimizing leakage loss. An ultra-low power standard cell library which uses this technique that achieves cancellation of leakage effects in both the PUN and PDN for CMOS circuits has been characterized for area, delay and power. A signal probability based self-controller was designed for leakage reduction. It is the core of this work that sequences the working of these sleep-embedded cells in any VLSI circuit. Comparison of our technique with other well-established leakage reduction techniques shows significant leakage savings of the former over the latter, with comparable area and delay performance degradation.