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Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow

Name: Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
Author: Colin J. Ihrig
ISBN: 9783639106909

AuthorColin J. Ihrig

PublisherVDM Verlag Dr. MÃ¼ller

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Book Details

Author(s)Colin J. Ihrig

PublisherVDM Verlag Dr. MÃ¼ller

ISBN / ASIN3639106903

ISBN-139783639106909

MarketplaceFrance 🇫🇷

Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow

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