Quantitative Evaluation of the Impact of Floating Point Arithmetic Units on the Performance of DSP Structures

Arithmetic operations traditionally used fixed-point processing because it makes them less expensive. In integer and fixed-point arithmetic, multipliers are larger, slower and consume much more power than adders, which are often neglected in performance evaluation of DSP systems. In floating-point arithmetic that is not true and in this thesis we show that multipliers and adders are equally important. The thesis also emphasizes low power design. Some of the basic digital filter network structures, built with FP arithmetic units, are revisited to map their performance with different filtering functions. It presents filter network structures transformed from their original form to accommodate pipe-lined arithmetic units. These filter structures can also be implemented with fixed-point arithmetic units because of the speed advantage they provide. Hardware synthesis of the structures, show that FIR filter Direct form sructure using an adder tree consumes less power than Direct form structure using a chain of adders and its transposed form. They also show that for IIR filters, Direct form II using standard floating-point arithmetic units is power optimal.