DESIGN AND IMPLEMENTATION OF SOFTWARE DEFIND RADIO MODEL BASED FPGA: FIR Digital Filter Design For SDR Using MATLAB, System Generator, ModelSim, Synplify Pro and ISE Environments from Xilinx

A key part of wireless communication system is the Digital Down Converter (DDC). It can be performed by a dedicated hardware in a processor. For example, when a GSM module is activated and connected to the internet via WLAN, It can be reconfigured in the chip which is used for the DDC to execute a lot of tasks. In this case the hardware has a high utilization factor. The algorithm can be performed continuously and only parameter settings might be changed. Any adaptability and spare performance will not be used in this situation Currently radio frequency (RF) transceivers demand a high integration devices as well as low cost and low power operations. The system is able to adapt into multiple communication standards such as software defined radio (SDR).