Low power hardware implementation of high speed FFT core.(Fast Fourier Transform)(Technical report): An article from: Journal of Computer Science
Book Details
Author(s)M. Kannan, S.K. Srivatsa
PublisherThomson Gale
ISBN / ASINB0012090P8
ISBN-13978B0012090P8
MarketplaceFrance 🇫🇷
Description
This digital document is an article from Journal of Computer Science, published by Thomson Gale on June 1, 2007. The length of the article is 3017 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.
From the author: Key words: Dual port RAM, shift register, finite state machine
Citation Details
Title: Low power hardware implementation of high speed FFT core.(Fast Fourier Transform)(Technical report)
Author: M. Kannan
Publication:Journal of Computer Science (Magazine/Journal)
Date: June 1, 2007
Publisher: Thomson Gale
Volume: 3 Issue: 5 Page: 376(7)
Article Type: Technical report
Distributed by Thomson Gale
From the author: Key words: Dual port RAM, shift register, finite state machine
Citation Details
Title: Low power hardware implementation of high speed FFT core.(Fast Fourier Transform)(Technical report)
Author: M. Kannan
Publication:Journal of Computer Science (Magazine/Journal)
Date: June 1, 2007
Publisher: Thomson Gale
Volume: 3 Issue: 5 Page: 376(7)
Article Type: Technical report
Distributed by Thomson Gale
