The present study provides a current review on the problems of self-test VLSI design. A summary is given on self-test VLSI design results that have been obtained by scientists in leading scientific centres for computer integrated circuits. Emphasis is placed on the theoretical fundamentals of designing self-test VLSI building blocks such as built-in test generators and output response analyzers. Particular attention is paid to: Structural design of self-test VLSI circuits; design of universal modules for self-test VLSI circuits; and examination of the VLSI circuits for signature testability. It has been clearly demonstrated that the design-for-testability techniques employed by this method provide ideal conditions for the straightforward implementation of self-test concepts. The work will prove essential reading for all those interested in both the basic facts and current research in this field.
Self-Testing VLSI Design
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Book Details
Author(s)V.N. Yarmolik, I.V. Kachan
PublisherElsevier Science
ISBN / ASIN0444896406
ISBN-139780444896407
Sales Rank15,932,913
CategoryComputers
MarketplaceUnited States 🇺🇸
Description ▲
A distinctive feature of modern computer equipment development is the continuous increase in functionality and complexity of computer components. As a result of these advances, very large-scale integration (VLSI) circuits have found extensive application in the manufacture of computer products, personal computers included. Among a variety of recently evolved VLSI design technologies, the self-test VLSI design has gained particular prominence.
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