Via modeling for high-speed simulations, Part 2: a method for creating via models and integrating into a network topology for high-speed PCB ... from: Printed Circuit Design & Manufacture
Book Details
Author(s)Abe Riazi
PublisherUP Media Group, Inc.
ISBN / ASINB0008E7WIG
ISBN-13978B0008E7WI7
AvailabilityAvailable for download now
Sales Rank13,730,972
MarketplaceUnited States 🇺🇸
Description
This digital document is an article from Printed Circuit Design & Manufacture, published by UP Media Group, Inc. on October 1, 2003. The length of the article is 1111 words. The page length shown above is based on a typical 300-word page. The article is delivered in HTML format and is available in your Amazon.com Digital Locker immediately after purchase. You can view it with any web browser.
Citation Details
Title: Via modeling for high-speed simulations, Part 2: a method for creating via models and integrating into a network topology for high-speed PCB simulations.(Interconnect Strategies)
Author: Abe Riazi
Publication:Printed Circuit Design & Manufacture (Magazine/Journal)
Date: October 1, 2003
Publisher: UP Media Group, Inc.
Volume: 20 Issue: 10 Page: 38(2)
Distributed by Thomson Gale
Citation Details
Title: Via modeling for high-speed simulations, Part 2: a method for creating via models and integrating into a network topology for high-speed PCB simulations.(Interconnect Strategies)
Author: Abe Riazi
Publication:Printed Circuit Design & Manufacture (Magazine/Journal)
Date: October 1, 2003
Publisher: UP Media Group, Inc.
Volume: 20 Issue: 10 Page: 38(2)
Distributed by Thomson Gale
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